Most modern processors are capable of performing arithmetic operations on values represented in floating-point notation. Floating-point arithmetic operations, including addition, subtraction, multiplication, division, and square root, are executed by an FPU within the processor. Floating-point arithmetic is often the foundation of graphics processing performed by both central processing units (CPU) and GPUs. IEEE Standard 754, developed by the Institute of Electrical and Electronic Engineers, sets forth the standard for binary floating-point arithmetic operation. IEEE 754 compliance and the efficiency of floating-point computations have received increasing attention as the demand for accelerated graphics processing has increased.
In the context of binary computers, a floating-point number is represented as a sign (a digit or string of digits representing a plus or minus), a mantissa or significant (a string of digits representing a number that is multiplied by a base of two raised by an exponent), and an exponent (a string of digits representing a number that is to raise a base of two). IEEE defines several floating-point formats varying in terms of the precision they represent. The total space allocated for representing a floating-point number can be, for example 32 bits, for single precision, or 64 bits, for double precision.
A correct implementation of IEEE 754 functionality requires algorithms designed to handle both normal and exception cases arising in floating-point arithmetic. Accordingly, modern FPUs typically employ distinct normal and exception computation paths, thus making path selection a critical stage in arithmetic execution. To satisfy the IEEE 754 standard, compliant FPUs are designed to recognize exception cases and then execute the exception path to produce the appropriate result, because an exception case processed via the normal path may produce an invalid result, a result that cannot be represented in floating-point notation, or possibly no result at all.